The invention pertains to input/output operations in a digital computer and specifically to a method of addressing memory for input/output operations in a digital computer.
In general input/output systems in a digital computer are dependent upon the central processing unit in a digital computer for operatin initiation and for address space allocation. Sometimes this is accomplished by transferring all input/output information from the input/output section of the digital computer to the central processing unit of the digital computer so that the central processing unit may access memory and store or retrieve data to or from memory to facilitate the input/output operation. In this event, the input/output section of the digital computer contains no facility for addressing memory which is separate from the central processing unit's memory addressing capability. Alternatively, input/output operations in a digital computer have been accomplished by allowing the input/output section of a digital computer to have direct access to the memory, an access which is in addition to the central processing unit's memory access. In this case, generally a specific address or plurality of addresses in main memory space are allocated to store certain state information necessary for the proper operation of the input/output channel. For example, at a particular address or particular set of addresses in memory a buffer control word may be stored to which the input/output section of the digital computer may refer to obtain an address to which the input/output section can utilize to buffer data to or from the memory to facilitate input/output operations. Thus, the input/output section of the digital computer has a separate dedicated space in memory which it and it alone may utilize. Generally this separate dedicated address space is fixed and unrelocatable.
Where it is necessary to connect a plurality of external devices to the input/output section of the digital computer generally these devices are connected to a separate input/output channel or subsection of the input/output section of the digital computer. In this event, where the input/output section of the digital computer has direct access to the main memory, each individual channel in the input/output section will have dedicated to it a separate address or set of addresses to utilize to store its buffer control information. Thus, in a multiple channel input/output operation a plurality of addresses or a plurality of sets of addresses are dedicated in main memory specifically for the use of the input/output section.
Where such direct memory access is allowed to the input/output section, the input/output section is generally still dependent upon the central processing unit for the initiation and control of its operations. That is, the central processing unit will supply commands and buffer and state information to the input/output section or to each individual channel within the input/output section. This information will govern, for example, the number of data words to be buffered, the number of bits contained in each data word, and the memory address to which or from which the data word or words are to be buffered. Once the input/output section or individual channel in the input/output section has the state information available the channel is then able to continue to perform the input/output buffering operation independently of the central processing unit.
In some situations it has been found to be necessary to connect a plurality of external devices to a single input/output channel in the input/output section of a digital computer. This is sometimes due to the extreme number of external devices that need to be connected to the digital computer and a general insufficiency in the number of input/output channels available. When multiple devices are connected to one input/output channel it is necessary, of course, to interleave the devices in some manner. Typically, the easiest way to perform this interleave is through a time sharing arrangement. That is, at any given point in time only one of the multiple devices may utilize the input/output channel and all other devices connected to that input/output channel must remain silent. In this way the multiple devices may take their turn and access the input/output channel consecutively.
This multiple connection of external devices to one input/output channel does cause some problem, however, in that generally only one set of state information is provided by a separate dedicated memory space allocation to each individual input/output channel. While multiple devices utilize one input/output channel they must be allowed to buffer into separate and distinct areas of memory. In order to perform this separation and buffering additional provision must be made by the external device in addition to the state information provided by the control processing unit.
One method of providing this additional information is through the use of externally specified addressing. When externally specified addressing is utilized for an input/output channel the external device will supply the input/output channel, in addition to a data word, an address at which to store or retrieve the data to be buffered. This externally specified address then designates the address in main memory to which or from which the data is to be buffered and may be utilized either separately or in conjunction with the state information provided to that input/output channel from the central processing unit.
This type of input/output operation and this type of externally specified addressing with respect to input/output operations is old in the art. An example of this general input/output organization is described and explained in U.S. Pat. No. 3,243,781, C. W. Ehrman, et al, entitled Digital Communication System. An example of this type of externally specified addressing is described in U.S. Pat. No. 3,251,040, R. L. Burkholder, et al, Computer Input-Output System. An understanding of both the Ehrman and Burkholder patents is basic to understanding the operation of the present invention. Accordingly, U.S. Pat. No. 3,243,781 and U.S. Pat. No. 3,251,040 are hereby incorporated by reference.
Understanding the present invention also involves understanding the basis of virtual addressing.
Virtual addressing is a form or a means for providing relative addressing. A virtual address specifies not a fixed location in main memory but rather a relative address in main memory. Virtual addressing is typically utilized or provided in cases where more addressing capability is provided than is necessary in immediate access main memory. In this way memory addressing may be provided for storage which is less direct than the main memory access unit as for example a backup disk, drum, tape or other bulk storage medium.
Heretofore in digital computer systems virtual addressing techniques have generally been confined to memory access involving central processing units. In digital computers where memory access is allowed both the central processing unit and the input/output section, virtual addressing has been provided generally only toward the access of memory provided by the central processing unit. The input/output section access to main memory generally still utilizes real, absolute, fixed main memory addresses. Since real addresses are still utilized by the input/output section, a separate memory space fixed in main memory is allocated to each input/output channel.
One example of a virtual address scheme which may be utilized is described in U.S. Pat. No. 4,128,875, filed Dec. 16, 1976 and issued Dec. 5, 1978, entitled Optional Virtual Memory System by K. J. Thurber, et al. Since the virtual memory system described in this U.S. Patent Application is basic to the understanding of the present invention, it is hereby incorporated by reference.